The continual trend toward smaller transistor device size in modern integrated circuits has enabled faster transistor operation and correspondingly faster signal propagation speeds within those circuits. Most modern computing devices utilize memory circuitry to store data required for device operation. These computing devices include combinational logic circuitry that depends upon timely receipt of data that is read from the memory circuitry. Therefore, as the speed of signal propagation through the combinational logic circuitry increases by way of the smaller transistor device size, it is possible that the memory access circuitry can become a signal timing bottleneck within the computing device. In memory circuits, a memory access speed in performing a read operation may be limited by the speed at which a requested memory address can be decoded and transformed into an appropriate wordline signal. It is of interest to improve memory access speed to mitigate the effects of memory access circuitry as a signal timing bottleneck. It is within this context that the present invention arises.